Doctoral Defense - Mikayla Benson

About the Event

The Department of Electrical and Computer Engineering 

Michigan State University 

Ph.D. Dissertation Defense 

Wednesday, May 7th, 2025, at 1:00 pm 

Electrical and Computer Engineering Conference Room EB 2219 and Zoom

Contact Department or Advisor for Zoom Information

ABSTRACT

NEUTRAL-POINT-LESS MULTILEVEL INVERTER WITH A SINGLE DC-LINK CAPACITOR

By: Mikayla Benson

Advisor: Dr. Woongkul “Matt” Lee

Multilevel inverters (MLIs) offer promising solutions for meeting the rising voltage requirements in electric transportation applications. Advances in MLI technology have enhanced power density, performance, and power ratings in inverter design. A topological analysis led to the proposal of neutral-point-less (NPL) inverters, which address challenges in traditional MLIs by redesigning the topology to eliminate key sources of harmonics, voltage imbalances, and electromagnetic interference (EMI). 

The operating principles of NPL.H and NPL.X inverters were introduced and compared with conventional MLIs using a duality approach. The findings showed that load impedance-based voltage division enables multilevel voltage generation without the stacked capacitors common in traditional MLIs. NPL inverters employ active neutral point generation rather than static capacitor-based neutral point, decoupling the neutral point current from the dc-link capacitor and inverter current. This approach reduces harmonics in the output voltage and current, along with ripple in the dc-link voltage and current.  An analytical method for load-based voltage generation in NPL.H and NPL.X inverters was presented and confirmed through simulation and experiment.  The NPL inverters also generate active common-mode voltage (CMV) cancellation to achieve a high-level of common-mode electromagnetic interference (CM EMI) noise. The NPL inverter topologies generate two equal and opposite CMVs. These features enable a significant CM EMI noise reduction, through active CMV cancellation. 

Due to the elimination of the stacked capacitors, the source of imbalance within the inverter topology is fundamentally different.  Since the NPL inverters rely solely on load impedance for voltage division, the voltage level imbalances are dependent on inductive dynamics, versus the capacitive dynamics found in conventional MLIs.  The effect of an imbalanced load is explored via equivalent impedance in connected load networks, generating a simple scaling factor to calculate the achievable half voltage level with load imbalance.  Imbalance in load can lead to voltage overshoot in the switching transition, which quickly settles to the half voltage level.  Offset in achievable voltage levels are minimal, at approximately 5% of the dc-link voltage, with nominally imbalanced.  Additionally, the EMI noise reduction performance is highly dependent on the symmetricity of two equal and opposite CMV waveforms, which can be distorted under unbalanced load conditions, and its influence is analyzed using incrementally increased imbalance in the load. Simulation and experimental results reveal that, while CMV cancellation is not perfect, the NPL.H inverter is still able to achieve a major reduction in CMV. 

Various modulation methods can be utilized to improve dc-link capacitor voltage and current ripple.  However, traditional MLIs require a neutral point connection with split capacitors which can cause capacitor voltage imbalance and overstress on devices due to the neutral current injection that can be made worse with various modulation methods. With the elimination of the capacitor-based neutral point, the effect of modulation methods on NPL inverters can be explored. A simple high-order form algorithm analytically investigates dc-link capacitor voltage and current ripple in NPL inverters.  The inverter was studied using two simple methods of carrier-based space vector pulse width modulation: phase opposition disposition (POD) and phase disposition (PD). PD modulation was consistently lower in dc-link capacitor rms and voltage ripple than POD modulation method at various operating conditions.  Additionally, simple carrier-based Discontinuous pulse width modulation (DPWM) methods were re-evaluated for the NPL inverters. DPWM is advantageous in reducing switching transitions and power losses, but it increases DC-link voltage and current ripple due to the neutral point connection in conventional MLIs.  It was found that DPWM2 reduces harmonics and improves efficiency in NPL inverters by decreasing switching events, as validated through simulations and experiments. 

Persons with disabilities have the right to request and receive reasonable accommodation. Please call the Department of Electrical and Computer Engineering at 355-5066 at least one day prior to the seminar; requests received after this date will be met when possible.